CoWoS chip-on-wafer-on-substrate packaging by TSMC
CoWoS, empaquetado de chips sobre oblea de TSMC
- Date
- 2011-2012 · confidence medium
- Place
- Hsinchu, Taiwan
- Credited to
- TSMC
- Field
- Knowledge & symbols
What it is
A packaging technique that places several chips (processor and high-bandwidth memory) on a silicon interposer attached to a substrate. It was used in 2012 for a Xilinx FPGA and is today the basis of artificial-intelligence accelerators.
TSMC announced CoWoS in 2011 and it was first applied in 2012 with Xilinx; silicon interposers and 2.5D stacking have antecedents in earlier research.
What it led to
- AI accelerators with HBM memory
- heterogeneous chip integration (chiplets)
- packaging-capacity bottlenecks in the AI industry