Planar process
Proceso planar de fabricación de semiconductores
- Date
- 1959 · confidence high
- Place
- Fairchild Semiconductor, Mountain View, California, United States
- Credited to
- Jean Hoerni (Fairchild Semiconductor)
- People
- 👤 Jean Hoerni1924–1997
- Field
- Matter & energy
What it is
Technique that fabricates transistors on a flat silicon surface protected by oxide, with diffusion through photolithographic masks. It made chip fabrication reproducible and scalable.
What it led to
- Photolithography as the engine of Moore's law
- The wafer-fabrication model and semiconductor foundries
- Silicon Valley's leadership and its spin-off companies (Intel, AMD)
Built on
- Bipolar junction transistor1948
- silicon oxide passivation
- photolithography
Made possible
- Monolithic silicon integrated circuit (Noyce)1959
- MOSFET (metal-oxide-semiconductor field-effect transistor)1959
- FinFET (3D transistor)2011
- Extreme ultraviolet lithography2019
- Noyce's monolithic integrated circuit
- EUV lithography